In a typical computer system, a core logic circuit such as a chipset, is widely used to control data flows among a central processing unit (CPU), a system memory and a plurality of input/output (I/O) devices. Recently, the processing frequency of the core logic circuit is increasingly improved. The speeds of data flows on the I/O buses, however, could not catch up with the step of the chipset. The major factors include the design of transmitters/receivers, type of package, construction of substrates and routing of circuit boards, for example. Therefore, the limitation of the I/O buses on bandwidth is required to be overcome.
A Double Data Rate (DDR) transmitter 10, with reference to FIGS. 1(a) and 1(b), was developed to meet these needs. The DDR transmitter 10 outputs data at both the rising and falling edges of a clock signal CK_0. Since data transmission are performed twice for each cycle of the clock signal CK_0, the data throughput doubles.
The transmitter 10 principally comprises two flip-flop devices 12 and 14, a multiplexer 16 and a pad circuit 18. First, three clock signals CK_90, CK_180 and CK_270 having the same frequency as the clock signal CK_0 are generated by a phase-locked loop circuit (not shown). The phase differences between these clock signals CK_90, CK_180 and CK_270 and the clock signal CK_0 are 90, 180 and 270 degrees, respectively. The flip-flop device 14 is latched in response to the rising edge of the clock signal CK_90, and sequentially outputs low-bit data DL including the first, the third, . . . , and the (2J+1) data as output data DXL, where J is an integer. The flip-flop device 12 is latched in response to the rising edge of the clock signal CK_270, and sequentially outputs high-bit data DH including the second, the fourth . . . , and the (2J)th data as output data DXH. The multiplexer 16 selects one of the two output data DXH and DXL from the flip-flop devices 12 and 14, respectively, to be outputted as output data TX_D to the pad circuit 18. The multiplexer 16 allows the output data DXH and DXL to be alternately outputted in response to a select signal, i.e. the clock signal CK_0. When the clock signal CK_0 turns to a low level, the low-bit data DXL is selected as the output data TX_D. On the other hand, when the clock signal CK_0 turns to a high level, the multiplexer 16 selects the high-bit data DXH to be the output data TX_D. Therefore, the data TX_D is outputted at a double data rate.
As is known, the valid data bit time for transmitting data on an I/O bus depends on the clock signal. In order to obtain precise and uniform valid data bit time, it is important to acquire a clock signal with a balanced duty cycle, i.e. 50%. The clock signal for the present purpose is generally provided by a clock generator and outputted by a phase-locked loop circuit. The clock signal of a 50% duty cycle provides the data flowing through the bus a unified data bit time. Unfortunately, it is difficult to control the duty cycle of the clock signal to be exactly 50% all the time. In general, the duty cycle of the clock signal outputted by the phase-locked loop circuit has a variation between about 48% and about 52%. Therefore, the use of the clock signal CK_0 with unbalanced duty cycle as a select signal of the multiplexer 16 will lead to inconsistent data bit time on the I/O bus. Thus, the setup/hold time margin will greatly decrease. Furthermore, when the data transfer speed on the bus is required to be higher and higher, it is even difficult to design a phase-locked loop circuit capable of providing various clock signals with a variety of phase differences.